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RISC-V@lemmy.mlEnglish · 8 months ago

Leaked docs hint Google may use SiFive RISC-V cores in next-gen TPUs

www.theregister.com

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Leaked docs hint Google may use SiFive RISC-V cores in next-gen TPUs

www.theregister.com

ylai@lemmy.ml to

RISC-V@lemmy.mlEnglish · 8 months ago

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Leaked doc suggest Google may buy more SiFive cores for TPUs

www.theregister.com

Would put those AI accelerators out of Arm's reach, at least

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RISC-V (pronounced “risk-five”) is a license-free, modular, extensible instruction set architecture (ISA).

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